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E2B0015-27-Y2
Semiconductor MSM9004-03/04
Semiconductor
This version: Nov. 1997 MSM9004-03/04 Previous version: Mar. 1996
1/4 DUTY LCD DRIVER WITH 4-DOT COMMON DRIVER AND 50-DOT SEGMENT DRIVER
GENERAL DESCRIPTION
The MSM 9004-03/04 is an LCD driver for dynamic display with a 1/4 duty and 50-dot segment driver. It can display up to 200 segments.
FEATURES
* Logic power supply voltage (VDD) * LCD drive power supply voltage (VLCD) * Serial transfer clock frequency * LCD output resistance Common driver Segment driver * Display duty * LCD segment output * Maximum number of display segments * Display blanking terminal attached * Operating temperature range * Interface with microcontroller MSM9004-03 MSM9004-04 * System clock MSM9004-03 MSM9004-04 * Package: 64-pin plastic QFP (QFP 64-P-1414-0.80-BK) : 5.0 V 10% : 3.7 V to 5.5 V : 2 MHz max. : 20 kW : 60 kW : 1/4 : 50 : 200 segments max. : -40 to +85C : LOAD, DATA, CLOCK1, CLOCK2 : LOAD, DATA, CLOCK2 : external input : internal oscillation circuit (external resistor and capacitor required) (Product name : MSM9004-03GS-BK) (Product name : MSM9004-04GS-BK)
* Comparison of device codes with functions
Function LCD segment output Device code MSM9004-01 MSM9004-02 MSM9004-03 MSM9004-04 50 -- -- -- -- -- -- -- -- -- 49 1/3 Duty 1/4 System clock External input Internal oscillation circuit --
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BLOCK DIAGRAM
MSM9004-03
SEG1 VDD BLANK VLC1 VLC2 VLC3 COM1 COM2 COM3 COM4 SEG50
50-DOT SEGMENT DRIVER
TIMING GENERATOR
50-BIT DATA SELECTOR
COMMON DRIVER
50-BIT DATA LATCH 1
50-BIT DATA LATCH 2
50-BIT DATA LATCH 3
50-BIT DATA LATCH 4
VDD CLOCK1 LOAD CLOCK2 DATA 50-BIT SHIFT REGISTER CONTROL LOGIC VSS
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BLOCK DIAGRAM
MSM9004-04
SEG1 VDD BLANK VLC1 VLC2 VLC3 COM1 COM2 COM3 COM4 SEG50
50-DOT SEGMENT DRIVER
TIMING GENERATOR
50-BIT DATA SELECTOR
COMMON DRIVER
50-BIT DATA LATCH 1
50-BIT DATA LATCH 2
50-BIT DATA LATCH 3
50-BIT DATA LATCH 4
VDD OSC LOAD CLOCK2 DATA OSCILLATOR CONTROL LOGIC 50-BIT SHIFT REGISTER VSS
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PIN CONFIGURATION (TOP VIEW)
56 CLOCK1 52 CLOCK2
MSM9004-03
51 BLANK
50 SEG50
49 SEG49
48 SEG48 47 SEG47 46 SEG46 45 SEG45 44 SEG44 43 SEG43 42 SEG42 41 SEG41 40 SEG40 39 SEG39 38 SEG38 37 SEG37 36 SEG36 35 SEG35 34 SEG34 33 SEG33
64 COM4
63 COM3
62 COM2
61 COM1
54 LOAD SEG27 27
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
1 2 3 4 5 6 7 8 9
SEG10 10 SEG11 11 SEG12 12 SEG13 13 SEG14 14 SEG15 15 SEG16 16
SEG17 17
SEG18 18
SEG19 19
SEG20 20
SEG21 21
SEG22 22
SEG23 23
SEG24 24
SEG25 25
SEG26 26
SEG28 28
53 DATA
60 VLC1
59 VLC2
58 VLC3
55 VDD
57 VSS
SEG29 29
SEG30 30
SEG31 31
64-Pin Plastic QFP
SEG32 32
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PIN CONFIGURATION (TOP VIEW)
MSM9004-04
52 CLOCK2
51 BLANK
50 SEG50
49 SEG49
48 SEG48 47 SEG47 46 SEG46 45 SEG45 44 SEG44 43 SEG43 42 SEG42 41 SEG41 40 SEG40 39 SEG39 38 SEG38 37 SEG37 36 SEG36 35 SEG35 34 SEG34 33 SEG33
64 COM4
63 COM3
62 COM2
61 COM1
54 LOAD SEG27 27
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
1 2 3 4 5 6 7 8 9
SEG10 10 SEG11 11 SEG12 12 SEG13 13 SEG14 14 SEG15 15 SEG16 16
SEG17 17
SEG18 18
SEG19 19
SEG20 20
SEG21 21
SEG22 22
SEG23 23
SEG24 24
SEG25 25
SEG26 26
SEG28 28
53 DATA
60 VLC1
59 VLC2
58 VLC3
56 OSC
55 VDD
57 VSS
SEG29 29
SEG30 30
SEG31 31
64-Pin Plastic QFP
SEG32 32
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PIN DESCRIPTIONS
Pin 56 56 Symbol CLOCK1 *1 OSC *2 Type Connected to I I Microcontroller External resistor Capacitor System clock input pin. For details see "MSM9004-04 Oscillation Circuit characteristics". Pin for oscillation. Connecting the external resistor and capacitor to configure the oscillation circuit. Connect the resistor and capacitor as shown in the right figure. Make the length of wiring between this pin and the external resistor and capacitor as short as possible. 53 52 54 DATA CLOCK2 LOAD I I I Microcontroller Microcontroller Microcontroller Serial data input. For details on the configuration of input data, see "Data Configuration". Shift clock input (Schmitt circuit included). Input data is read synchronizing with the rising edge of this clock. Load signal input (Schmitt circuit included). Serial input data is transferred to the display latch when this LOAD signal is at a "H" level. 51 BLANK I -- 61 to 64 COM1-4 1 to 50 SEG1-50 60 59 58 VLC1 VLC2 VLC3 O O Power supply -- LCD LCD Input pin for turning off all segments. All segments turn off, regardless of the display data, when this pin is at a "L" level, and all segments return to the status before turning off. LCD common output pins. LCD segment output pins. Bias power supply pins for driving the LCD. Conditions for bias voltage are as follows : 3.7V VDD - VLC3 5.5V 2 VLC1 = VDD - 3 (VDD - VLC3) 1 VLC2 = VDD - 3 (VDD - VLC3) VLC3 VSS 55 57 VDD VSS Power supply -- Power supply pins. Normally used as VDD = 4.5 to 5.5 V and Vss = 0 V. VSS OSC VDD Description
*1 Applied to MSM9004-03. *2 Applied to MSM9004-04.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage LCD Driving Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VLCD VIN PD TSTG Condition -- -- -- Ta = +85C -- Rating -0.3 to +6.5 -0.3 to VDD +0.3 -0.3 to VDD +0.3 450 -55 to +150 Unit V V V mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage LCD Driving Voltage System Clock Frequency Self Oscillation Frequency Shift Frequency (Max) Operating Temperature Symbol VDD VLCD * 1 fCP1 fOSC fCP2 Top Condition -- *2 Applied to MSM9004-01 Applied to MSM9004-02 -- -- Range 4.5 to 5.5 3.7 to VDD 1.5 to 4.3 1.5 to 4.3 2.0 -40 to +85 *3 Unit V V kHz kHz MHz C
*1: *2:
*3:
VDD-VLC3 The following relationship must be kept: VDD>VLC1>VLC2VSS VLC1=VDD - 1 (VDD - VLC3) 3 VLC2=VDD - 2 (VDD - VLC3) 3 VLC3=VDD - 3 (VDD - VLC3) 3 VDD is the reference potential for the LCD driving voltage. To decide the LCD driving voltage, change the voltage between VLC3 and VSS (VLC3 > 0).
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ELECTRICAL CHARACTERISTICS
DC Characteristics (MSM9004-03)
(Ta= - 40 to +85C, VDD=4.5 to 5.5 V, VDD-VLC3= 3.7 V to VDD) Parameter "H" Input Voltage Symbol VIH1 VIH2 "L" Input Voltage VIL1 VIL2 "H" Input Current IIH1 IIH2 "L" Input Current IIL1 IIL2 RON V0 ON Resistance (SEG) RON V1 RON V2 RON V3 RON V0 ON Resistance (COM) RON V1 RON V2 RON V3 Condition -- -- -- -- VIN=VDD VIN=VDD VDD=5.5 V, VIN=0 V VDD=5.5 V, VIN=0 V IO=-10 mA IO=10 mA IO=10 mA IO=10 mA IO=-30 mA IO=30 mA IO=30 mA IO=30 mA fCP1=2.4 kHz fCP2=1 MHz Dynamic Supply Current IDD 1/4 duty COM1-4: No Load SEG1-50: No Load -- 0.65 mA VDD *1 VDD=4.5 V 2 VLC1= VDD 3 1 VLC2= 3 VDD VLC3=VSS -- 20 kW COM1-4 -- 60 kW SEG1-50 Min. Max. Unit Applicable pin 0.8VDD 0.85VDD 0.0 0.0 -1.0 -3.0 -1.0 -160 VDD VDD 0.2VDD 0.15VDD 1.0 3.0 1.0 -20 V V V V mA mA mA mA LOAD, CLOCK2 DATA, BLANK CLOCK1 LOAD, CLOCK2 DATA, BLANK CLOCK1 LOAD, CLOCK1 CLOCK2, DATA BLANK LOAD, CLOCK1 CLOCK2, DATA BLANK
* 1:
For input data, input a logic "0" and a logic "1" to LCD display bits alternately. The tr and tf time for the CLOCK1, CLOCK2, DATA, and LOAD pins must be less than 20ns.
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Semiconductor DC Characteristics (MSM9004-04)
MSM9004-03/04
(Ta= - 40 to +85C, VDD=4.5 to 5.5 V, VDD-VLC3= 3.7 V to VDD) Parameter "H" Input Voltage "L" Input Voltage "H" Input Current Symbol VIH1 VIL1 IIH1 IIH2 "L" Input Current IIL1 IIL2 RON V0 ON Resistance (SEG) RON V1 RON V2 RON V3 RON V0 ON Resistance (COM) RON V1 RON V2 RON V3 Condition -- -- VIN=VDD VIN=VDD VDD=5.5 V, VIN=0 V VDD=5.5 V, VIN=0 V IO=-10 mA IO=10 mA IO=10 mA IO=10 mA IO=-30 mA IO=30 mA IO=30 mA IO=30 mA fCP2=1 MHz Dynamic Supply Current IDD 1/4 duty COM1-4: No Load SEG1-50: No Load *1 -- 1.00 mA VDD VDD=4.5 V 2 VLC1= VDD 3 VLC2= 1 V 3 DD -- 20 kW COM1-4 -- 60 kW SEG1-50 Min. Max. Unit Applicable pin 0.8VDD 0.0 -1.0 -3.0 -1.0 -160 VDD 0.2VDD 1.0 3.0 1.0 -20 V V mA mA mA mA LOAD, CLOCK2 DATA, BLANK LOAD, CLOCK2 DATA, BLANK LOAD, CLOCK2 DATA BLANK LOAD, CLOCK2 DATA BLANK
VLC3=VSS
* 1:
For input data, input a logic "0" and a logic "1" to LCD display bits alternately. External resistor for oscillation : RO = 62 kW External copacitor for oscillation : CO = 0.01 mF The tr and tf time for the CLOCK2, DATA, and LOAD pins must be less than 20ns. The current that flows through the external resistor and capacitor is not included.
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MSM9004-03/04
(Ta= - 40 to +85C, VDD=4.5 to 5.5 V, VDD-VLC3= 3.7 V to VDD) Parameter System Clock Frequency System Clock Pulse Width Data Clock Frequency Data Clock Pulse Width Data Setup Time Data Hold Time Load Pulse Width Clock-Load Time Load-Clock Time Rise Time Fall Time Symbol fCP1 tWCP1 fCP2 tWCP2 tSU tHD tWLD tCL tLC tr tf Condition Not applied to MSM9004-04 Not applied to MSM9004-04 -- -- -- -- -- -- -- -- -- Min. 1.5 1.0 -- 200 100 100 200 200 200 -- -- Max. 4.3 -- 2.0 -- -- -- -- -- -- 100 100 Unit kHz ms MHz ns ns ns ns ns ns ns ns
twCP1 tr
twCP1 tf 0.85VDD
CLOCK1 *1 tr twCP2 twCP2 tf 1/fCP1
0.15VDD
0.8VDD CLOCK2 tSU tHD 1/fCP2 0.8VDD DATA tr tf tWLD tCL tr tf tLC 0.8VDD 0.2VDD 0.2VDD 0.2VDD
LOAD
*1 Not applied to MSM9004-04.
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FUNCTIONAL DESCRIPTION
Display Data Input
CLOCK2 DATA D50 D49 D48 D47 D46 LCD display bit (50 bits) D3 D2 D1 0 0 C1 C2 C3 C4
LOAD
Dummy bit (2 bits)
Select bit (4 bits)
Note:
Always set a logic "0" to the dummy bit.
LCD Display bit - LCD Panel Lighting Status Correspondence Table
LCD display bit (D1 to D50) 1 0 LCD panel lighting status ON OFF
LCD Display bit - Segment Output Correspondence Table
LCD display bit Segment output D1 SEG1 D2 SEG2 D46 SEG46 D47 SEG47 D48 SEG48 D49 SEG49 D50 SEG50
Select bit - Data Latch Correspondence Table
C4 0 0 0 1 C3 0 0 1 0 C2 0 1 0 0 C1 1 0 0 0 Display data writing data latch Data latch 1 Data latch 2 Data latch 3 Data latch 4 Corresponding common output COM1 COM2 COM3 COM4
Select bits C1 to C4 select Data latch 1 to Data latch 4 corresponding to COM 1 to COM 4 independently. If logic "1s" are selected to multiple select bits, the LCD display bits are written to all corresponding data latches. Example: When logic "1s" are set to all select bits C1 to C4, and logic "0s" are set to all LCD display bits D1 to D50, logic "0s" are written to Data latch 1 to Data latch 4 by one data input. This leads to turning off the entire LCD panel.
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How to Decrease Transfer Time When Unused Segments Exist The MSM9004-03/04 can operate even if segment data is not full. Input data as in the figure shown below. In this case, the last 4 bits are the select bits. Transfer example: for 30 segments
CLOCK2 DATA D30 D29 D28 D27 D26 LCD display bits (30 bits) D2 D1 0 0 C1 C2 C3 C4
LOAD
Dummy bits (2 bits)
Select bits (4 bits)
Note:
Always set "0" to the dummy bit.
Recommended RC Values for MSM9004-04 Oscillation Circuit Shown below are the recommended oscillation resistor (RO) and capacitor (CO) values for providing frame frequency fFRM of approximately 62 Hz to 190 Hz. * RO = 62 kW 5% * CO = 0.01 mF 5% (Resistance and capacitance variations due to temperature change are not included.) For requirements of supply voltage (VDD), ambient temperature range (Ta), and frame frequency (fFRM): * VDD = 5.0 V * Ta = -40 to +85C * fFRM = 1 oscillation frequency 24
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APPLICATION CIRCUITS
MSM9004-03
+5 V VDD
VDD DATA Output Port CLOCK2 LOAD
SEG1
CPU
VSS
CLOCK1 BLANK
1/4 DUTY LCD PANEL MSM9004-03
BIAS CIRCUIT
VLC1 VLC2 VLC3 SEG50 COM1 COM2 COM3 COM4
VSS
MSM9004-04
+5 V VDD
VDD DATA Output Port CLOCK2 LOAD
SEG1
CPU
VSS BLANK
1/4 DUTY LCD PANEL MSM9004-04
BIAS CIRCUIT
VLC1 VLC2 VLC3 OSC SEG50 COM1 COM2 COM3 COM4
R0
C0 VSS
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REFERENCE DATA
fFRM vs. R0
Frame Frequency fFRM [Hz]
500 300 100 50 30 10
VDD = 5 V Ta = 25C
CO = 0.01 mF CO = 0.015 mF CO = 0.022 mF
20
40
60
80
Resistance RO [kW]
140 Frame Frequency fFRM [Hz] 120 100 80 60 40 20 -40
fFRM vs. Ta
VDD = 5 V RO = 33 kW CO = 0.015 mF RO = 62 kW CO = 0.01 mF RO = 62 kW CO = 0.015 mF
-10 0
25
85
Temperature Ta [C]
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PACKAGE DIMENSIONS
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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